
arraypoint:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400480 <_init>:
  400480:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400484:	910003fd 	mov	x29, sp
  400488:	94000030 	bl	400548 <call_weak_fn>
  40048c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400490:	d65f03c0 	ret

Disassembly of section .plt:

00000000004004a0 <.plt>:
  4004a0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4004a4:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf334>
  4004a8:	f947fe11 	ldr	x17, [x16, #4088]
  4004ac:	913fe210 	add	x16, x16, #0xff8
  4004b0:	d61f0220 	br	x17
  4004b4:	d503201f 	nop
  4004b8:	d503201f 	nop
  4004bc:	d503201f 	nop

00000000004004c0 <__libc_start_main@plt>:
  4004c0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004c4:	f9400211 	ldr	x17, [x16]
  4004c8:	91000210 	add	x16, x16, #0x0
  4004cc:	d61f0220 	br	x17

00000000004004d0 <__gmon_start__@plt>:
  4004d0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004d4:	f9400611 	ldr	x17, [x16, #8]
  4004d8:	91002210 	add	x16, x16, #0x8
  4004dc:	d61f0220 	br	x17

00000000004004e0 <abort@plt>:
  4004e0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004e4:	f9400a11 	ldr	x17, [x16, #16]
  4004e8:	91004210 	add	x16, x16, #0x10
  4004ec:	d61f0220 	br	x17

00000000004004f0 <printf@plt>:
  4004f0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004f4:	f9400e11 	ldr	x17, [x16, #24]
  4004f8:	91006210 	add	x16, x16, #0x18
  4004fc:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400500 <_start>:
  400500:	d280001d 	mov	x29, #0x0                   	// #0
  400504:	d280001e 	mov	x30, #0x0                   	// #0
  400508:	aa0003e5 	mov	x5, x0
  40050c:	f94003e1 	ldr	x1, [sp]
  400510:	910023e2 	add	x2, sp, #0x8
  400514:	910003e6 	mov	x6, sp
  400518:	580000c0 	ldr	x0, 400530 <_start+0x30>
  40051c:	580000e3 	ldr	x3, 400538 <_start+0x38>
  400520:	58000104 	ldr	x4, 400540 <_start+0x40>
  400524:	97ffffe7 	bl	4004c0 <__libc_start_main@plt>
  400528:	97ffffee 	bl	4004e0 <abort@plt>
  40052c:	00000000 	.inst	0x00000000 ; undefined
  400530:	004009ac 	.word	0x004009ac
  400534:	00000000 	.word	0x00000000
  400538:	004009c8 	.word	0x004009c8
  40053c:	00000000 	.word	0x00000000
  400540:	00400a48 	.word	0x00400a48
  400544:	00000000 	.word	0x00000000

0000000000400548 <call_weak_fn>:
  400548:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf334>
  40054c:	f947f000 	ldr	x0, [x0, #4064]
  400550:	b4000040 	cbz	x0, 400558 <call_weak_fn+0x10>
  400554:	17ffffdf 	b	4004d0 <__gmon_start__@plt>
  400558:	d65f03c0 	ret
  40055c:	00000000 	.inst	0x00000000 ; undefined

0000000000400560 <deregister_tm_clones>:
  400560:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400564:	9100c000 	add	x0, x0, #0x30
  400568:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40056c:	9100c021 	add	x1, x1, #0x30
  400570:	eb00003f 	cmp	x1, x0
  400574:	540000a0 	b.eq	400588 <deregister_tm_clones+0x28>  // b.none
  400578:	90000001 	adrp	x1, 400000 <_init-0x480>
  40057c:	f9453421 	ldr	x1, [x1, #2664]
  400580:	b4000041 	cbz	x1, 400588 <deregister_tm_clones+0x28>
  400584:	d61f0020 	br	x1
  400588:	d65f03c0 	ret
  40058c:	d503201f 	nop

0000000000400590 <register_tm_clones>:
  400590:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400594:	9100c000 	add	x0, x0, #0x30
  400598:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40059c:	9100c021 	add	x1, x1, #0x30
  4005a0:	cb000021 	sub	x1, x1, x0
  4005a4:	9343fc21 	asr	x1, x1, #3
  4005a8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4005ac:	9341fc21 	asr	x1, x1, #1
  4005b0:	b40000a1 	cbz	x1, 4005c4 <register_tm_clones+0x34>
  4005b4:	90000002 	adrp	x2, 400000 <_init-0x480>
  4005b8:	f9453842 	ldr	x2, [x2, #2672]
  4005bc:	b4000042 	cbz	x2, 4005c4 <register_tm_clones+0x34>
  4005c0:	d61f0040 	br	x2
  4005c4:	d65f03c0 	ret

00000000004005c8 <__do_global_dtors_aux>:
  4005c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4005cc:	910003fd 	mov	x29, sp
  4005d0:	f9000bf3 	str	x19, [sp, #16]
  4005d4:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  4005d8:	3940c260 	ldrb	w0, [x19, #48]
  4005dc:	35000080 	cbnz	w0, 4005ec <__do_global_dtors_aux+0x24>
  4005e0:	97ffffe0 	bl	400560 <deregister_tm_clones>
  4005e4:	52800020 	mov	w0, #0x1                   	// #1
  4005e8:	3900c260 	strb	w0, [x19, #48]
  4005ec:	f9400bf3 	ldr	x19, [sp, #16]
  4005f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4005f4:	d65f03c0 	ret

00000000004005f8 <frame_dummy>:
  4005f8:	17ffffe6 	b	400590 <register_tm_clones>

00000000004005fc <v>:
  4005fc:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400600:	910003fd 	mov	x29, sp
  400604:	90000000 	adrp	x0, 400000 <_init-0x480>
  400608:	9129e000 	add	x0, x0, #0xa78
  40060c:	d2800503 	mov	x3, #0x28                  	// #40
  400610:	d2800102 	mov	x2, #0x8                   	// #8
  400614:	d2800021 	mov	x1, #0x1                   	// #1
  400618:	97ffffb6 	bl	4004f0 <printf@plt>
  40061c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400620:	9129e000 	add	x0, x0, #0xa78
  400624:	d2800103 	mov	x3, #0x8                   	// #8
  400628:	d2800022 	mov	x2, #0x1                   	// #1
  40062c:	d2800021 	mov	x1, #0x1                   	// #1
  400630:	97ffffb0 	bl	4004f0 <printf@plt>
  400634:	d503201f 	nop
  400638:	a8c47bfd 	ldp	x29, x30, [sp], #64
  40063c:	d65f03c0 	ret

0000000000400640 <array>:
  400640:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400644:	910003fd 	mov	x29, sp
  400648:	910043a0 	add	x0, x29, #0x10
  40064c:	90000001 	adrp	x1, 400000 <_init-0x480>
  400650:	912ec021 	add	x1, x1, #0xbb0
  400654:	4c40a020 	ld1	{v0.16b, v1.16b}, [x1]
  400658:	4c00a000 	st1	{v0.16b, v1.16b}, [x0]
  40065c:	910043a0 	add	x0, x29, #0x10
  400660:	91002000 	add	x0, x0, #0x8
  400664:	910043a1 	add	x1, x29, #0x10
  400668:	91002022 	add	x2, x1, #0x8
  40066c:	910043a5 	add	x5, x29, #0x10
  400670:	90000001 	adrp	x1, 400000 <_init-0x480>
  400674:	912a6024 	add	x4, x1, #0xa98
  400678:	aa0203e3 	mov	x3, x2
  40067c:	aa0003e2 	mov	x2, x0
  400680:	aa0503e1 	mov	x1, x5
  400684:	aa0403e0 	mov	x0, x4
  400688:	97ffff9a 	bl	4004f0 <printf@plt>
  40068c:	910043a0 	add	x0, x29, #0x10
  400690:	91001000 	add	x0, x0, #0x4
  400694:	910043a4 	add	x4, x29, #0x10
  400698:	90000001 	adrp	x1, 400000 <_init-0x480>
  40069c:	912b0023 	add	x3, x1, #0xac0
  4006a0:	aa0003e2 	mov	x2, x0
  4006a4:	aa0403e1 	mov	x1, x4
  4006a8:	aa0303e0 	mov	x0, x3
  4006ac:	97ffff91 	bl	4004f0 <printf@plt>
  4006b0:	910043a0 	add	x0, x29, #0x10
  4006b4:	91001000 	add	x0, x0, #0x4
  4006b8:	910043a4 	add	x4, x29, #0x10
  4006bc:	90000001 	adrp	x1, 400000 <_init-0x480>
  4006c0:	912ba023 	add	x3, x1, #0xae8
  4006c4:	aa0003e2 	mov	x2, x0
  4006c8:	aa0403e1 	mov	x1, x4
  4006cc:	aa0303e0 	mov	x0, x3
  4006d0:	97ffff88 	bl	4004f0 <printf@plt>
  4006d4:	910043a1 	add	x1, x29, #0x10
  4006d8:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006dc:	912c4000 	add	x0, x0, #0xb10
  4006e0:	97ffff84 	bl	4004f0 <printf@plt>
  4006e4:	910043a0 	add	x0, x29, #0x10
  4006e8:	b9400001 	ldr	w1, [x0]
  4006ec:	90000000 	adrp	x0, 400000 <_init-0x480>
  4006f0:	912c8000 	add	x0, x0, #0xb20
  4006f4:	97ffff7f 	bl	4004f0 <printf@plt>
  4006f8:	910043a0 	add	x0, x29, #0x10
  4006fc:	b9400001 	ldr	w1, [x0]
  400700:	90000000 	adrp	x0, 400000 <_init-0x480>
  400704:	912ce000 	add	x0, x0, #0xb38
  400708:	97ffff7a 	bl	4004f0 <printf@plt>
  40070c:	910043a0 	add	x0, x29, #0x10
  400710:	b9400001 	ldr	w1, [x0]
  400714:	90000000 	adrp	x0, 400000 <_init-0x480>
  400718:	912d4000 	add	x0, x0, #0xb50
  40071c:	97ffff75 	bl	4004f0 <printf@plt>
  400720:	910043a0 	add	x0, x29, #0x10
  400724:	b9400001 	ldr	w1, [x0]
  400728:	90000000 	adrp	x0, 400000 <_init-0x480>
  40072c:	912da000 	add	x0, x0, #0xb68
  400730:	97ffff70 	bl	4004f0 <printf@plt>
  400734:	910043a0 	add	x0, x29, #0x10
  400738:	b9401401 	ldr	w1, [x0, #20]
  40073c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400740:	912de000 	add	x0, x0, #0xb78
  400744:	97ffff6b 	bl	4004f0 <printf@plt>
  400748:	910043a0 	add	x0, x29, #0x10
  40074c:	91005000 	add	x0, x0, #0x14
  400750:	b9400001 	ldr	w1, [x0]
  400754:	90000000 	adrp	x0, 400000 <_init-0x480>
  400758:	912e4000 	add	x0, x0, #0xb90
  40075c:	97ffff65 	bl	4004f0 <printf@plt>
  400760:	52800000 	mov	w0, #0x0                   	// #0
  400764:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400768:	d65f03c0 	ret

000000000040076c <array_point>:
  40076c:	a9ba7bfd 	stp	x29, x30, [sp, #-96]!
  400770:	910003fd 	mov	x29, sp
  400774:	9101a3a0 	add	x0, x29, #0x68
  400778:	d100c000 	sub	x0, x0, #0x30
  40077c:	90000001 	adrp	x1, 400000 <_init-0x480>
  400780:	912ec021 	add	x1, x1, #0xbb0
  400784:	4c40a020 	ld1	{v0.16b, v1.16b}, [x1]
  400788:	4c00a000 	st1	{v0.16b, v1.16b}, [x0]
  40078c:	9100e3a0 	add	x0, x29, #0x38
  400790:	f9002fa0 	str	x0, [x29, #88]
  400794:	9101a3a0 	add	x0, x29, #0x68
  400798:	d1014000 	sub	x0, x0, #0x50
  40079c:	9100e3a1 	add	x1, x29, #0x38
  4007a0:	f9000001 	str	x1, [x0]
  4007a4:	9101a3a0 	add	x0, x29, #0x68
  4007a8:	d1014000 	sub	x0, x0, #0x50
  4007ac:	9100e3a1 	add	x1, x29, #0x38
  4007b0:	f9000001 	str	x1, [x0]
  4007b4:	9101a3a0 	add	x0, x29, #0x68
  4007b8:	d100c000 	sub	x0, x0, #0x30
  4007bc:	b9400000 	ldr	w0, [x0]
  4007c0:	93407c00 	sxtw	x0, w0
  4007c4:	aa0003e1 	mov	x1, x0
  4007c8:	9101a3a0 	add	x0, x29, #0x68
  4007cc:	d1014000 	sub	x0, x0, #0x50
  4007d0:	f9000001 	str	x1, [x0]
  4007d4:	9101a3a0 	add	x0, x29, #0x68
  4007d8:	d1014000 	sub	x0, x0, #0x50
  4007dc:	9100e3a1 	add	x1, x29, #0x38
  4007e0:	f9000001 	str	x1, [x0]
  4007e4:	9100e3a0 	add	x0, x29, #0x38
  4007e8:	91002002 	add	x2, x0, #0x8
  4007ec:	9100e3a1 	add	x1, x29, #0x38
  4007f0:	90000000 	adrp	x0, 400000 <_init-0x480>
  4007f4:	912f4000 	add	x0, x0, #0xbd0
  4007f8:	97ffff3e 	bl	4004f0 <printf@plt>
  4007fc:	f9402fa0 	ldr	x0, [x29, #88]
  400800:	91002001 	add	x1, x0, #0x8
  400804:	90000000 	adrp	x0, 400000 <_init-0x480>
  400808:	912fa000 	add	x0, x0, #0xbe8
  40080c:	aa0103e2 	mov	x2, x1
  400810:	f9402fa1 	ldr	x1, [x29, #88]
  400814:	97ffff37 	bl	4004f0 <printf@plt>
  400818:	f9402fa0 	ldr	x0, [x29, #88]
  40081c:	91001001 	add	x1, x0, #0x4
  400820:	90000000 	adrp	x0, 400000 <_init-0x480>
  400824:	91300000 	add	x0, x0, #0xc00
  400828:	aa0103e2 	mov	x2, x1
  40082c:	f9402fa1 	ldr	x1, [x29, #88]
  400830:	97ffff30 	bl	4004f0 <printf@plt>
  400834:	f9402fa0 	ldr	x0, [x29, #88]
  400838:	91001001 	add	x1, x0, #0x4
  40083c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400840:	91308000 	add	x0, x0, #0xc20
  400844:	aa0103e2 	mov	x2, x1
  400848:	f9402fa1 	ldr	x1, [x29, #88]
  40084c:	97ffff29 	bl	4004f0 <printf@plt>
  400850:	f9402fa0 	ldr	x0, [x29, #88]
  400854:	91002001 	add	x1, x0, #0x8
  400858:	90000000 	adrp	x0, 400000 <_init-0x480>
  40085c:	91310000 	add	x0, x0, #0xc40
  400860:	97ffff24 	bl	4004f0 <printf@plt>
  400864:	f9402fa0 	ldr	x0, [x29, #88]
  400868:	b9400001 	ldr	w1, [x0]
  40086c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400870:	91314000 	add	x0, x0, #0xc50
  400874:	97ffff1f 	bl	4004f0 <printf@plt>
  400878:	f9402fa0 	ldr	x0, [x29, #88]
  40087c:	b9400001 	ldr	w1, [x0]
  400880:	90000000 	adrp	x0, 400000 <_init-0x480>
  400884:	91318000 	add	x0, x0, #0xc60
  400888:	97ffff1a 	bl	4004f0 <printf@plt>
  40088c:	f9402fa0 	ldr	x0, [x29, #88]
  400890:	b9400001 	ldr	w1, [x0]
  400894:	90000000 	adrp	x0, 400000 <_init-0x480>
  400898:	9131c000 	add	x0, x0, #0xc70
  40089c:	97ffff15 	bl	4004f0 <printf@plt>
  4008a0:	f9402fa0 	ldr	x0, [x29, #88]
  4008a4:	91004000 	add	x0, x0, #0x10
  4008a8:	b9400401 	ldr	w1, [x0, #4]
  4008ac:	90000000 	adrp	x0, 400000 <_init-0x480>
  4008b0:	91320000 	add	x0, x0, #0xc80
  4008b4:	97ffff0f 	bl	4004f0 <printf@plt>
  4008b8:	f9402fa0 	ldr	x0, [x29, #88]
  4008bc:	91004000 	add	x0, x0, #0x10
  4008c0:	91001000 	add	x0, x0, #0x4
  4008c4:	b9400001 	ldr	w1, [x0]
  4008c8:	90000000 	adrp	x0, 400000 <_init-0x480>
  4008cc:	91324000 	add	x0, x0, #0xc90
  4008d0:	97ffff08 	bl	4004f0 <printf@plt>
  4008d4:	52800000 	mov	w0, #0x0                   	// #0
  4008d8:	a8c67bfd 	ldp	x29, x30, [sp], #96
  4008dc:	d65f03c0 	ret

00000000004008e0 <evaluate>:
  4008e0:	d10143ff 	sub	sp, sp, #0x50
  4008e4:	910083e0 	add	x0, sp, #0x20
  4008e8:	f9001fe0 	str	x0, [sp, #56]
  4008ec:	910083e0 	add	x0, sp, #0x20
  4008f0:	f9001fe0 	str	x0, [sp, #56]
  4008f4:	910083e0 	add	x0, sp, #0x20
  4008f8:	f9001fe0 	str	x0, [sp, #56]
  4008fc:	910083e0 	add	x0, sp, #0x20
  400900:	f90027e0 	str	x0, [sp, #72]
  400904:	910023e0 	add	x0, sp, #0x8
  400908:	f90027e0 	str	x0, [sp, #72]
  40090c:	9100e3e0 	add	x0, sp, #0x38
  400910:	f90023e0 	str	x0, [sp, #64]
  400914:	f94023e0 	ldr	x0, [sp, #64]
  400918:	910083e1 	add	x1, sp, #0x20
  40091c:	f9000001 	str	x1, [x0]
  400920:	f94023e0 	ldr	x0, [sp, #64]
  400924:	910023e1 	add	x1, sp, #0x8
  400928:	f9000001 	str	x1, [x0]
  40092c:	910023e0 	add	x0, sp, #0x8
  400930:	f90023e0 	str	x0, [sp, #64]
  400934:	d503201f 	nop
  400938:	910143ff 	add	sp, sp, #0x50
  40093c:	d65f03c0 	ret

0000000000400940 <_tmain>:
  400940:	d10243ff 	sub	sp, sp, #0x90
  400944:	b9000fe0 	str	w0, [sp, #12]
  400948:	f90003e1 	str	x1, [sp]
  40094c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400950:	9132a001 	add	x1, x0, #0xca8
  400954:	9100a3e0 	add	x0, sp, #0x28
  400958:	a9400c22 	ldp	x2, x3, [x1]
  40095c:	a9000c02 	stp	x2, x3, [x0]
  400960:	a9410c22 	ldp	x2, x3, [x1, #16]
  400964:	a9010c02 	stp	x2, x3, [x0, #16]
  400968:	b9402021 	ldr	w1, [x1, #32]
  40096c:	b9002001 	str	w1, [x0, #32]
  400970:	9101c3e0 	add	x0, sp, #0x70
  400974:	f9000be0 	str	x0, [sp, #16]
  400978:	910183e0 	add	x0, sp, #0x60
  40097c:	f9000fe0 	str	x0, [sp, #24]
  400980:	910143e0 	add	x0, sp, #0x50
  400984:	f90013e0 	str	x0, [sp, #32]
  400988:	9101c3e0 	add	x0, sp, #0x70
  40098c:	f90047e0 	str	x0, [sp, #136]
  400990:	9100a3e0 	add	x0, sp, #0x28
  400994:	f90047e0 	str	x0, [sp, #136]
  400998:	910043e0 	add	x0, sp, #0x10
  40099c:	f90043e0 	str	x0, [sp, #128]
  4009a0:	52800000 	mov	w0, #0x0                   	// #0
  4009a4:	910243ff 	add	sp, sp, #0x90
  4009a8:	d65f03c0 	ret

00000000004009ac <main>:
  4009ac:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4009b0:	910003fd 	mov	x29, sp
  4009b4:	97ffff23 	bl	400640 <array>
  4009b8:	52800000 	mov	w0, #0x0                   	// #0
  4009bc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4009c0:	d65f03c0 	ret
  4009c4:	00000000 	.inst	0x00000000 ; undefined

00000000004009c8 <__libc_csu_init>:
  4009c8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4009cc:	910003fd 	mov	x29, sp
  4009d0:	a901d7f4 	stp	x20, x21, [sp, #24]
  4009d4:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf334>
  4009d8:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf334>
  4009dc:	91374294 	add	x20, x20, #0xdd0
  4009e0:	913722b5 	add	x21, x21, #0xdc8
  4009e4:	a902dff6 	stp	x22, x23, [sp, #40]
  4009e8:	cb150294 	sub	x20, x20, x21
  4009ec:	f9001ff8 	str	x24, [sp, #56]
  4009f0:	2a0003f6 	mov	w22, w0
  4009f4:	aa0103f7 	mov	x23, x1
  4009f8:	9343fe94 	asr	x20, x20, #3
  4009fc:	aa0203f8 	mov	x24, x2
  400a00:	97fffea0 	bl	400480 <_init>
  400a04:	b4000194 	cbz	x20, 400a34 <__libc_csu_init+0x6c>
  400a08:	f9000bb3 	str	x19, [x29, #16]
  400a0c:	d2800013 	mov	x19, #0x0                   	// #0
  400a10:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400a14:	aa1803e2 	mov	x2, x24
  400a18:	aa1703e1 	mov	x1, x23
  400a1c:	2a1603e0 	mov	w0, w22
  400a20:	91000673 	add	x19, x19, #0x1
  400a24:	d63f0060 	blr	x3
  400a28:	eb13029f 	cmp	x20, x19
  400a2c:	54ffff21 	b.ne	400a10 <__libc_csu_init+0x48>  // b.any
  400a30:	f9400bb3 	ldr	x19, [x29, #16]
  400a34:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400a38:	a942dff6 	ldp	x22, x23, [sp, #40]
  400a3c:	f9401ff8 	ldr	x24, [sp, #56]
  400a40:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400a44:	d65f03c0 	ret

0000000000400a48 <__libc_csu_fini>:
  400a48:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400a4c <_fini>:
  400a4c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400a50:	910003fd 	mov	x29, sp
  400a54:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400a58:	d65f03c0 	ret
